@article {peternier2012CPE,
	title = {High Performance Execution of Service Compositions: a Multicore-aware Engine Design},
	journal = {Concurrency and Computation: Practice and Experience (CPE)},
	volume = {26},
	year = {2014},
	month = {January},
	pages = {71-97},
	publisher = {Wiley},
	abstract = {Although modern computer hardware offers an increasing number of processing elements organized in nonuniform memory access (NUMA) architectures, prevailing middleware engines for executing business processes, workflows, and Web service compositions have not been optimized for properly exploiting the abundant processing resources of such machines. Amongst others, factors limiting performance are inefficient thread scheduling by the operating system, which can result in suboptimal use of system memory and CPU caches, and sequential code sections that cannot take advantage of multiple available cores.
In this article, we study the performance of the JOpera process execution engine on recent multicore machines. We first evaluate its performance without any dedicated optimization for multicore hardware, showing that additional cores do not significantly improve performance, although the engine has a multithreaded design. Therefore, we apply optimizations on the basis of replication together with an improved, hardware-aware usage of the underlying resources such as NUMA nodes and CPU caches. Thanks to our optimizations, we achieve speedups from a factor of 2 up to a factor of 20 (depending on the target machine) when compared with a baseline execution {\textquoteleft}as is{\textquoteright}. },
	keywords = {JOpera, multicores, nonuniform memory access architecture, performance optimization, service composition and execution},
	doi = {10.1002/cpe.2948},
	author = {Achille Peternier and Walter Binder and Cesare Pautasso and Daniele Bonetta}
}
@article {105,
	title = {Improving execution unit occupancy on SMT-based processors through hardware-aware thread scheduling},
	journal = {Future Generation Computer Systems},
	volume = {30},
	year = {2014},
	month = {January},
	pages = {229 - 241},
	abstract = {Modern processor architectures are increasingly complex and heterogeneous, often requiring software solutions tailored to the specific hardware characteristics of each processor model. In this article, we address this problem by targeting two processors featuring Simultaneous MultiThreading (SMT) to improve the occupancy of their internal execution units through a sustained stream of instructions coming from more than one thread. We target the AMD Bulldozer and IBM POWER7 processors as case studies for specific hardware-oriented performance optimizations that increase the variety of instructions sent to each core to maximize the occupancy of all its execution units. WorkOver, presented in this article, improves thread scheduling by increasing the performance of floating point-intensive workloads on Linux-based operating systems. WorkOver is a user-space monitoring tool that automatically identifies FPU-intensive threads and schedules them in a more efficient way without requiring any patches or modifications at the kernel level. Our measurements using standard benchmark suites show that speedups of up to 20\% can be achieved by simply allowing WorkOver to monitor applications and schedule their threads, without any modification of the workload.},
	keywords = {multicores, Overseer},
	issn = {0167739X},
	doi = {10.1016/j.future.2013.06.015},
	author = {Achille Peternier and Danilo Ansaloni and Daniele Bonetta and Cesare Pautasso and Walter Binder}
}
@conference {jopera:2010:soca,
	title = {Exploiting multicores to optimize business process execution},
	booktitle = {International Conference on Service-Oriented Computing and Applications (SOCA 2010)},
	year = {2010},
	month = {December},
	pages = {1-8},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Perth, Australia},
	abstract = {While modern CPUs offer an increasing number of cores with shared caches, prevailing execution engines for business processes, workflows, or Web service compositions have not been optimized for properly exploiting the abundant processing resources of such CPUs. One factor limiting performance is the inefficient thread scheduling by the operating system, which can result in suboptimal use of shared caches. In this paper we study performance of the JOpera business process execution engine on a recent multicore machine. By analyzing the engine{\textquoteright}s architecture and by binding threads that are likely to access shared data to cores with a common cache, we achieve speedups up to 13\% for a variety of workloads, without modifying the engine{\textquoteright}s architecture and implementation, apart from binding threads to CPUs. As the engine is implemented in Java, we provide a new Java library to manage thread bindings and hardware performance counters. We also leverage hardware performance counters to explain the observed speedup in our performance analysis.},
	keywords = {business data processing, business process execution engines, business process execution optimization, hardware performance counters, Java, JOpera, multicores, performance optimization, thread-CPU bindings, Web service composition, Web services, workflow},
	doi = {10.1109/SOCA.2010.5707156},
	author = {Achille Peternier and Daniele Bonetta and Cesare Pautasso and Walter Binder}
}
@conference {jopera:2010:apscc,
	title = {A Multicore-Aware Runtime Architecture for Scalable Service Composition},
	booktitle = {5th Asia-Pacific Services Computing Conference (APSCC 2010)},
	year = {2010},
	month = {December},
	pages = {83-90},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Hangzhou, China},
	abstract = {Middleware for web service orchestration, such as runtime engines for executing business processes, workflows, or web service compositions, can easily become performance bottlenecks when the number of concurrent service requests increases. Many existing process execution engines have been designed to address scalability with distribution and replication techniques. However, the advent of modern multicore machines, comprising several chip multi-processors each offering multiple cores and often featuring a large shared cache, offers the opportunity to redesign the architecture of process execution engines in order to take full advantage of the underlying hardware resources. In this paper we present an innovative process execution engine architecture. Its design takes into account the specific constraints of multicore machines and scales well on different processor architectures, as shown by our extensive performance evaluation. A key feature of the design is self-configuration at startup according to the type and number of available CPUs. We show that our design makes efficient use of the available resources and can scale to run thousands of concurrent business process instances per second, highlighting the potential and the benefits for multicore-awareness in the design of scalable process execution engines.},
	keywords = {middleware, multicore-aware runtime architecture, multicores, process execution engine, Web service composition, Web services},
	doi = {10.1109/APSCC.2010.61},
	author = {Daniele Bonetta and Achille Peternier and Cesare Pautasso and Walter Binder}
}
